1. Field of the Invention
The present invention pertains to the field of integrated circuit memory cells and, particularly, ferroelectric devices that are used as components in nonvolatile memories. More specifically, the ferroelectric devices include ferroelectric capacitors and field effect transistors that are resistant to disturb voltage pulses.
2. Statement of the Problem
Ferroelectric materials are used in nonvolatile memories because they have the ability to retain information for long periods of time. Ferroelectrics polarize in the presence of an applied field and subsequently retain a polarized state for an indefinite period of time after the field is removed. The class of ferroelectrics including the layered superlattice materials described in WO 93/12542 in the name of Araujo et al., in thin film form, can retain sufficient polarization to perform memory operations for approximately ten years or more after the ferroelectrics have been polarized and the field has been removed.
The ability of ferroelectric memories to retain stored data is, in actuality, much shorter than the period of time the ferroelectric alone is capable of retaining polarization, due to the manner in which memories must operate. Current proposed ferroelectric memory architecture designs require the ferroelectrics to withstand small unintended voltage pulses as nearby capacitors are being read or written. These small voltage pulses are referred to in the art as "disturb" voltages. For example, experimental results show a lead zirconium titanate (PZT) capacitor can withstand approximately 10.sup.8 repetitions of a 0.4 volt (V) disturb voltage pulse with a 10% loss in retained polarization. Polarization degrades much more rapidly for larger pulses with 10.sup.8 cycles at 1 V causing an approximate two-thirds loss in retained polarization.
FIG. 1 shows a disturb voltage loss for a capacitor including a layered superlattice material, i.e., strontium bismuth tantalate. Polarization losses due to disturb voltages are similar to the losses in PZT, i.e., a normalized percentage for retained polarization projects to an approximate two-thirds loss after 10.sup.8 unidirectional cycles at 1 V. Present state-of-the-art memories utilize a write pulse of about 3 V. FIG. 1 indicates that even for a disturb voltage that is one-tenth of the state-of-the-art write voltages, that is even for disturb voltages of 0.3 V, the polarization is significantly degraded.
WO 93/12542 shows a ferroelectric random access memory (FERAM) cell consisting of a conventional field effect transistor and a ferroelectric capacitor. The bottom electrode of the capacitor is connected to a transistor active area in the manner of a conventional 1T 1C dynamic random access memory (DRAM) cell. In reference to FIGS. 3C and 3D of WO 93/12542, the transistor gate is connected to the word line, and the transistor source area is connected to the bit line. The transistor drain area is connected to the bottom electrode of a ferroelectric capacitor where data is stored. The bit line and word line are driven to high and low voltages for read and write operations, which subject the ferroelectric material to disturb voltages. Over time, these disturb voltages degrade the ferroelectric polarization until memory operations can no longer be performed, unless the memory storage state is read and rewritten in a refresh operation similar to that for conventional DRAMS.
Nakamura et al., "A Single-Transistor Ferroelectric Memory Cell", IEEE p. 68 (1995) shows a single transistor memory cell; i.e., a ferroelectric floating gate random access memory (FFRAM) having a gate that is formed as a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure. The device uses a floating gate formed of conventional silicon. The silicon bottom gate is used as the bottom electrode, and a ferroelectric layer is grown on top of the gate. A first electrode resides atop the ferroelectric layer. The charge of the gate is controlled by using a first electrode to polarize the ferroelectric. The localized field of the polarized ferroelectric is used to alter the threshold voltage across the transistor source/drain regions. The memory cell may be enhanced by the addition of a back gate, which is used as a bit line and held at a programming voltage, i.e., a voltage sufficient to cause ferroelectric switching. The first electrode is used as the word line and held at one-half the programming voltage. Other FFRAM transistors have been made including an MFMIS gate formed of a vertical sequence including silicon dioxide, polysilicon, iridium oxide, lead zirconium titanate, iridium oxide, and iridium. The use of an MFMIS gate in FFRAM cells does not eliminate problems that derive from disturb voltages because many cells are disturbed by variations in the voltage on either the word line or the bit line, as these lines are applied to the specific architecture of the MFMIS gate. There remains a need to protect ferroelectrics in integrated circuit memories from the effects of disturb voltages.
The FFRAM discussed above is one type of a ferroelectric field effect transistor or FFET. Other FFETS are disclosed in U.S. Pat. No. 5,523,964 issued Jun. 4, 1996 to McMillan et al. These FFETS, as well as other FFRAMS also suffer from the disturb problem to varying degrees.